The invention relates to emitter ballasted power transistors primarily intended for use in integrated circuit (IC) structures. My U.S. Pat. No. 4,441,116 describes a bipolar power transistor that is designed to operate at high collector voltage and is not subject to secondary breakdown. This is accomplished by a base ballasting arrangement using a junction field effect transistor incorporated into the power transistor base. However, the patent teaches the nature and virtues of emitter ballasting. This device, as well as most prior art power transistors, is intended primarily for discrete device structures. These employ a back-side collector contact that is also a heat sink which acts to absorb the heat generated within the power transistor. When a power transistor is incorporated into an IC structure, typically all of the device contacts must be located on one chip face. This substantially increases the problems of making electrical contact to the power transist or electrodes.
U.S. Pat. Nos. 4,136,354 and 4,146,903 issued to Robert C. Dobkin and are assigned to the assignee of the present invention. These patents describe a sense emitter incorporated into a power transistor device. The sense emitter is located close enough to the transistor power emitter so that the heat developed in the power transistor will be sensed. A remote emitter is employed as a reference so that a thermal gradient can be determined and employed to limit the power transistor conduction to a safe level.
U.S. Pat. No. 3,504,239 discloses a power transistor which employs a distributed resistor array that interconnects a plurality of separate emitters. The array also provides the desired emitter ballasting. Polycrystalline silicon is one suggested resistive material.